1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor memory device, and more particularly, to a method for etching a Pt film or layer which is used as a storage node of a capacitor of a semiconductor memory device.
2. Description of the Related Art
In general, as semiconductor memory devices (such as a dynamic random access memory (DRAM)) become more highly integrated, they require capacitors of high capacitance which occupy only a small area. To satisfy this integration requirement, a trench type or cylinder type capacitor has been developed which offers high capacitance with a relatively small surface area. Unfortunately, however, the trench type or cylinder type capacitor is difficult to form correctly and requires a complicated fabrication process. Therefore, using conventional technology, there are severe, practical limits to the realization of the desired high capacitance and high integration of the semiconductor memory device.
To solve the problems of fabrication difficulty and inconsistency, a method for forming a capacitor has been developed and widely utilized which uses barium strontium titanate (BST) as a dielectric of the capacitor. BST has a dielectric constant approximately 400 times higher than that of a conventional dielectric. When the capacitor is formed using a material having a high dielectric constant, such as BST, a platinum (Pt) layer is usually used as plate and storage nodes of the capacitor. Pt is used because it is a stable material and therefore does not oxidize at the surface of the dielectric during the high-temperature heat treatment required for forming the BST dielectric film. Moreover, Pt has excellent conductivity and therefore less leakage current is generated from the dielectric electrode of the capacitor than when other conductive films such as iridium (Ir), ruthenium (Ru), or polysilicon are used. One drawback of Pt, however, is that because it is a non-reactive metal, it does not react easily with other chemicals and is therefore very difficult to pattern using dry etching.
Due to this difficulty, halogen is usually used for etching the Pt layer in a process known as "reactive ion etching" (RIE). Unfortunately, because halogen reacts only weakly with Pt ions, the Pt layer is etched primarily by a physical reaction called "ion sputtering" rather than by a chemical reaction. As the Pt layer is etched by ion spluttcrinig, etchingy residues are generated which reduce the etching slope of the Pt layer and thereby result in Pt electrodes which do not have a fine pattern. A fine pattern of Pt electrodes is desirable because the BST capacitor will be used increasingly in fine pattern DRAM devices. Also, because of the difficulty in etching the Pt layer, the etch rate is generally low. A low etch rate is undesirable because it results in low throughput. In order to improve the low etch rate during reactive ion etching, an etching gas containing chlorine or fluorine is used because of the possibility of Pt compound formation.
A conventional method for etching the Pt layer, using chlorine gas as an etching gas, is disclosed in U.S. Pat. No. 5,515,984 "Method for etching Pt layer," issue date May, 14, 1996. According to this conventional method, chlorine and oxygen are used as an etching gas. Etching residues platinum chloride (PtCl) and platinum monoxide (PtO) arc correspondingly formed on the sidewalls of an etching resist film and the Pt layer is etched using the etching resist film and the etching residues as an etching mask. The etching residues are then removed by a process known as "wet etching." Despite the improvements offered by this technique over the other processes described above, the etching residues left by this process require appropriate removal, and the etching slope of the Pt layer is still less than desirable. As for the etching residue, it was revealed from experiments that most of the residue is pure aluminum rather than platinum compounds, so most of the residues cannot be removed by wet etching. The industry is therefore in need of a method for etching a Pt layer of a semiconductor device which results both in an improved etching slope of the Pt layer and in Pt electrodes having a finer pattern.